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cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 1 post office box 655303 ? dallas, texas 75265 generates clocks for pentium ? iii class microprocessors supports a single pentium iii microprocessor uses a 14.318 mhz crystal input to generate multiple output frequencies includes spread spectrum clocking (ssc), 0.34% downspread for reduced emi performance power management control terminals low output skew and jitter for clock distribution operates from dual 2.5-v and 3.3-v supplies generates the following clocks: 3 cpu (2.5 v, 100/133 mhz) 10 pci (3.3 v, 33.3 mhz) 1 cpu/2 (2.5 v, 50/66 mhz) 1 apic (2.5 v, 16.67 mhz) 3 3v66 (3.3 v, 66 mhz) 2 ref (3.3 v, 14.318 mhz) 1 48mhz (3.3 v, 48 mhz) packaged in 48-pin ssop package designed for use with ti's direct rambus ? clock generators (cdcr81, cdcr82, cdcr83) description the cdc922 is a clock synthesizer/driver that generates cpu, cpu_div2, 3v66, pci, apic, 48mhz, and ref system clock signals to support computer systems with a single pentium iii class microprocessor. all output frequencies are generated from a 14.318-mhz crystal input. instead of a crystal, a reference clock input can be provided at the xin input. two phase-locked loops (plls) are used to generate the host frequencies and the 48-mhz clock frequency. on-chip loop filters and internal feedback eliminate the need for external components. the host and pci clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. all outputs have 3-state capability, which can be selected via control inputs sel0, sel1, and sel133/100 . the 48mhz clock can be independently disabled via the control inputs sel0, sel1, and sel133/100 . in this state, the 48-mhz pll is disabled and the 48mhz clock is driven to high impedance to reduce component jitter. the outputs are either 3.3-v or 2.5-v single-ended cmos buffers. with a logic high-level on the pwr_dwn terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state. copyright ? 1999, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ref0 ref1 v dd 3.3v xin xout gnd pci0 pci1 v dd 3.3v pci2 pci3 pci4 pci5 gnd pci6 pci7 v dd 3.3v pci8 pci9 gnd 3v66(0) 3v66(1) 3v66(2) v dd 3.3v gnd v dd 2.5v apic gnd v dd 2.5v cpu_div2 gnd v dd 2.5v cpu2 gnd v dd 2.5v cpu1 cpu0 gnd v dd 3.3v gnd pwr_dwn spread sel1 sel0 v dd 3.3v 48mhz gnd sel133/100 dl package (top view) intel and pentium iii are trademarks of intel corporation. direct rambus and rambus are trademarks of rambus inc. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 2 post office box 655303 ? dallas, texas 75265 description (continued) the cpu bus can operate at 100 mhz or 133 mhz. output frequency selection is done with corresponding setting for sel133/100 control input. the pci bus frequency is fixed to 33 mhz. since the cdc922 is based on pll circuitry, it requires a stabilization time to achieve phase lock of the pll. this stabilization time is required after power up or after changes to the sel inputs are made. with use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts. function tables select functions inputs outputs sel133/ 100 sel1 sel0 cpu cpu_div2 3v66 pci 48mhz ref apic function l l l hi-z hi-z hi-z hi-z hi-z hi-z hi-z 3-state l l h n/a n/a n/a n/a n/a n/a n/a reserved l h l 100 mhz 50 mhz 66 mhz 33 mhz hi-z 14.318 mhz 16.67 mhz 48-mhz pll off l h h 100 mhz 50 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 16.67 mhz 48-mhz pll on h l l tclk/2 tclk/4 tclk/4 tclk/8 tclk/2 tclk tclk/16 test h l h n/a n/a n/a n/a n/a n/a n/a reserved h h l 133 mhz 66 mhz 66 mhz 33 mhz hi-z 14.318 mhz 16.67 mhz 48-mhz pll off h h h 133 mhz 66 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 16.67 mhz 48-mhz pll on enable functions inputs outputs internal pwr_dwn cpu cpu_div2 apic 3v66 pci ref, 48mhz crystal vcos l l l l l l l off off h on on on on on on on on output buffer specifications buffer name v dd range (v) impedance ( w ) buffer type cpu, cpu_div2, apic 2.375 2.625 13.5 45 type 1 48mhz, ref 3.135 3.465 20 60 type 3 pci, 3v66 3.135 3.465 12 55 type 5
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description 3v66 [02] 2123 o 3.3 v, type 5, 66-mhz clock outputs 48mhz 27 o 3.3 v, type 3, 48-mhz clock output apic 46 o 2.5 v, type 2, apic clock output at 16.67 mhz cpu [02] 36, 37, 40 o 2.5 v, type 1, cpu clock outputs cpu_div2 43 o 2.5 v, type 1, cpu_div2 clock output gnd 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 ground for pci, 3v66, 48mhz, cpu, cpu_div2, apic, ref [01] outputs and core pci [09] 7, 8, 1013, 15, 16, 18, 19 o 3.3 v, type 5, 33-mhz pci clock outputs pwr_dwn 32 i power down for complete device with outputs forced low ref0, ref1 1, 2 o 3.3 v, type 3, 14.318-mhz reference clock outputs sel0, sel1 29, 30 i lvttl level logic select terminals for function selection sel133/100 25 i lvttl level logic select terminal for enabling 100/133 mhz spread 31 i disables ssc function v dd 2.5v 38, 41, 44, 47 power for cpu, cpu_div2, and apic outputs v dd 3.3v 3, 9, 17, 24, 28, 34 power for the ref, pci, 3v66, 48mhz outputs and core xin 4 i crystal input 14.318 mhz xout 5 o crystal output 14.318 mhz
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 4 post office box 655303 ? dallas, texas 75265 spread spectrum clock (ssc) implementation for cdc922 simultaneously switching at fixed frequency generates a significant power peak at the selected frequency, which in turn will cause emi disturbance to the environment. the purpose of the internal frequency modulation of the cpupll allows to distribute the energy to many different frequencies which reduces the power peak. a typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in figure 1. highest peak non-ssc ssc d of f nom f nom d figure 1. frequency power spectrum with and without the use of ssc the modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a adown-spread modulationo. the peak reduction depends on the modulation scheme and modulation profile. system performance and timing requirements are the limiting factors for actual design implementations. the implementation was driven to keep the average clock frequency closed to its upper specification limit. the modulation amount was set to approximately 0.34% (compared to 0.5% on the cdc921). in order to allow a downstream pll to follow the frequency modulated signal, the bandwidth of the modulation signal is limited in order to minimize ssc induced tracking skew jitter. the ideal modulation profile used for cdc922 is shown in figure 2. 51015 2025303540 45 period of modulation signal m s 9.97 9.98 9.99 10 10.01 10.02 10.03 period of output frequency ns figure 2. ssc modulation profile
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 5 post office box 655303 ? dallas, texas 75265 functional block diagram 2*ref 14.318 mhz (1,2) sel133/100 pwr_dwn spread xout xin sel1 sel0 control logic 25 30 29 3-state sel 133/100 48-mhz inactive test xtal oscillator 5 4 48 mhz pll cpu pll spread logic sync logic & power down logic /2 /2 31 32 1*48mhz 48 mhz (27) 3*cpu 100/133 mhz (36,37,40) 10*pci 33 mhz (7,8,10,11,12, 13,15,16,18,19) 1*apic 16.67 mhz (46) 3*agp (3v66) 66 mhz (21,22,23) /3 /4 /2 /3 /4 1*cpu_div2 50/66 mhz (43)
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 6 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v dd 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high-impedance state or power-off state, v o (see note 1) 0.5 v to v dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into any output in the low state, i o 2 i ol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed . dissipation rating table package t a 25 c derating factor 2 t a = 70 c t a = 85 c package a power ratng above t a = 25 c a power rating a power rating dl 1315.7 mw 10.53 mw/ c 842.1 mw 684.2 mw 2 this is the inverse of the traditional junction-to-case thermal resistance (r q ja ) and uses a board-mounted device at 95 c/w. recommended operating conditions (see note 2) min nom 2 max unit su pp ly voltage v dd 3.3 v 3.135 3.465 v s u ppl y v oltage , v dd 2.5 v 2.375 2.625 v high-level input voltage, v ih 2 v dd + 0.3 v v low-level input voltage, v il gnd 0.3 v 0.8 v input voltage, v i 0 v dd v cpux, cpu_div2 12 high level out p ut current i oh apic 12 ma high - le v el o u tp u t c u rrent , i oh 48mhz, refx 14 ma pcix, pci_f, 3v66x 18 cpux, cpu_div2 12 low level out p ut current i ol apic 12 ma lo w- le v el o u tp u t c u rrent , i ol 48mhz, refx 9 ma pcix, pci_f, 3v66x 12 reference frequency, f (xtal) 3 test mode 130 mhz crystal frequency, f (xtal) normal mode 13.8 14.318 14.8 mhz operating free-air temperature, t a 0 85 c note 2: unused inputs must be held high or low to prevent them from floating. 2 all nominal values are measured at their respective nominal v dd values. 3 reference frequency is a test clock driven on the xin input during the device test mode and normal mode. in test mode, xin can be driven externally up to f (xtal) = 130 mhz. if xin is driven externally, xout is floating. this is a series fundamental crystal with f o = 14.31818 mhz.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 7 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit v ik input clamp voltage v dd = 3.135 v, i i = 18 ma 1.2 v r i input resistance xin, xout v dd = 3.465 v, v i = v dd 0.5 v 80 350 k w xout v dd = 3.135 v, v i = v dd 0.5 v 20 50 ma i ih high-level input current sel0, sel1, spread v dd = 3.465 v, v i = v dd <10 10 m a ih g pwr_dwn v dd = 3.465 v, v i = v dd <10 10 m a sel133/100 v dd = 3.465 v, v i = v dd <10 10 m a xout v dd = 3.135 v, v i = 0 v 2 5 ma i il low-level input current sel0, sel1, spread v dd = 3.465 v, v i = gnd <10 10 m a il pwr_dwn v dd = 3.465 v, v i = gnd <10 10 m a sel133/100 v dd = 3.465 v, v i = gnd <10 10 m a i oz high-impedance-state output current |v dd | = max, v o = v dd or gnd 10 m a v dd = 2.625 v, pwr_dwn = low all outputs = low, <20 100 m a i dd su pp ly current v dd = 2.625 v, all outputs = high <20 100 m a i dd s u ppl y c u rrent v dd = 3.465 v, pwr_dwn = low all outputs = low, <50 200 m a v dd = 3.465 v, all outputs = high 12 37 ma i dd(z) high-impedance-state supply v dd = 2.625 v 1.4 ma i dd(z) gy current v dd = 3.465 v 30 ma dynamic i dd c l = 20 pf, v dd = 3.465 v 114 156 ma d y namic i dd l cpu = 133 mhz v dd = 2.625 v 44 60 ma c i input capacitance v dd = 3.3 v, v i = v dd or gnd 3.3 5.8 pf crystal terminal capacitance v dd = 3.3 v, v i = 0.3 v 18 18.5 22.5 pf 2 all typical values are measured at their respective nominal v dd values.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 8 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) cpux, cpu_div2, apic (type 1) parameter test conditions min typ 2 max unit v oh hi g h-level output volta g e v dd = min to max, i oh = 1 ma vdd 0.1 v v oh gg v dd = 2.375 v, i oh = 12 ma 2 v ol low level out p ut voltage v dd = min to max, i ol = 1 ma 0.1 v v ol lo w- le v el o u tp u t v oltage v dd = 2.375 v, i ol = 12 ma 0.18 0.4 v v dd = 2.375 v, v o = 1 v 26 42 i oh high-level output current v dd = 2.5 v, v o = 1.25 v 46 ma v dd = 2.625 v, v o = 2.375 v 16 27 v dd = 2.375 v, v o = 1.2 v 27 57 i ol low-level output current v dd = 2.5 v, v o = 1.25 v 63 ma v dd = 2.625 v, v o = 0.3 v 23 43 c o output capacitance v dd = 3.3 v, v o = v dd or gnd 5.8 8.5 pf z o out p ut im p edance high state v o = 0.5 v dd , v o /i oh 13.5 27 45 w z o o u tp u t impedance low state v o = 0.5 v dd , v o /i ol 13.5 20 45 w 2 all typical values are measured at their respective nominal v dd values. 48mhz, refx (type 3) parameter test conditions min typ 2 max unit v oh high-level output voltage v dd = min to max, i oh = 1 ma vdd 0.1 v v oh gg v dd = 3.135 v, i oh = 14 ma 2.4 v ol low level out p ut voltage v dd = min to max, i ol = 1 ma 0.1 v v ol lo w- le v el o u tp u t v oltage v dd = 3.135 v, i ol = 9 ma 0.18 0.4 v v dd = 3.135 v, v o = 1 v 27 41 i oh high-level output current v dd = 3.3 v, v o = 1.65 v 41 ma v dd = 3.465 v, v o = 3.135 v 12 23 v dd = 3.135 v, v o = 1.95 v 29 50 i ol low-level output current v dd = 3.3 v, v o = 1.65 v 53 ma v dd = 3.465 v, v o = 0.4 v 20 37 c o output capacitance v dd = 3.3 v, v o = v dd or gnd 4.5 7 pf z o out p ut im p edance high state v o = 0.5 v dd , v o /i oh 20 40 60 w z o o u tp u t impedance low state v o = 0.5 v dd , v o /i ol 20 31 60 w 2 all typical values are measured at their respective nominal v dd values.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 9 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) pcix, 3v66x (type 5) parameter test conditions min typ 2 max unit v oh hi g h-level output volta g e v dd = min to max, i oh = 1 ma vdd 0.1 v v oh gg v dd = 3.135 v, i oh = 18 ma 2.4 v ol low level out p ut voltage v dd = min to max, i ol = 1 ma 0.1 v v ol lo w- le v el o u tp u t v oltage v dd = 3.135 v, i ol = 12 ma 0.15 0.4 v v dd = 3.135 v, v o = 1 v 33 53 i oh high-level output current v dd = 3.3 v, v o = 1.65 v 53 ma v dd = 3.465 v, v o = 3.135 v 16 33 v dd = 3.135 v, v o = 1.95 v 30 67 i ol low-level output current v dd = 3.3 v, v o = 1.65 v 70 ma v dd = 3.465 v, v o = 0.4 v 27 49 c o output capacitance v dd = 3.3 v, v o = v dd or gnd 4.5 7.5 pf z o out p ut im p edance high state v o = 0.5 v dd , v o /i oh 12 31 55 w z o o u tp u t impedance low state v o = 0.5 v dd , v o /i ol 12 24 55 w 2 all typical values are measured at their respective nominal v dd values. switching characteristics, v dd = 3.135 v to 3.465 v, t a = 0 c to 85 c parameter test conditions min typ max unit overshoot/undershoot gnd 0.7 v v dd + 0.7 v v ring back v il 0.1 v v ih + 0.1 v v stabilization time, pwr_dwn to pcix f (cpu) = 133 mhz 0.05 3 ms t dis3 disable time, pwr_dwn to pcix f (cpu) = 133 mhz 50 ns stabilization time, pwr_dwn to cpux f (cpu) = 133 mhz 0.03 3 ms t dis4 disable time, pwr_dwn to cpux f (cpu) = 133 mhz 50 ns stabilization time 2 after sel1, sel0 3 ms stabili z ation time 2 after power up 3 ms 2 stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its refer ence signal. in order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at x1. until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. stabilization time is defined as the time from when v dd achieves its nominal operating level until the output frequency is stable and operating within specification.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 10 post office box 655303 ? dallas, texas 75265 switching characteristics, v dd = 2.375 v to 2.625 v, t a = 0 c to 85 c (continued) cpux parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 cpux f (cpu) = 100 or 133mhz 6 10 ns t dis1 output disable time sel133/100 cpux f (cpu) = 100 or 133mhz 8 10 ns t cpu clock period 2 f (cpu) = 100 mhz 10 10.04 10.2 ns t c cpu c l oc k per i o d 2 f (cpu) = 133 mhz 7.5 7.53 7.7 ns cycle to cycle jitter f (cpu) = 100 or 133mhz 250 ps duty cycle f (cpu) = 100 or 133mhz 45 55 % t sk(o) cpu bus skew cpux cpux f (cpu) = 100 or 133mhz 50 175 ps t sk(p) cpu pulse skew cpun cpun f (cpu) = 100 or 133mhz 2.2 ns t (off) cpu clock to apic clock offset, rising edge 1.5 2.8 4 ns t (off) cpu clock to 3v66 clock offset, rising edge 0 0.75 1.5 ns t 1 pulse duration width high f (cpu) = 100 mhz 2.6 4.3 ns t w1 p u lse d u ration w idth , high f (cpu) = 133 mhz 1.4 3.7 ns t 2 pulse duration width low f (cpu) = 100 mhz 2.8 4.3 ns t w2 p u lse d u ration w idth , lo w f (cpu) = 133 mhz 1.7 4 ns t r rise time v o = 0.4 v to 2.0 v 0.4 1.5 2.2 ns t f fall time v o = 0.4 v to 2.0 v 0.4 1.4 2 ns 2 the average over any 1- m s period of time is greater than the minimum specified period. cpu_div2 parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 cpu_div2 f (cpu) = 100 or 133mhz 6 10 ns t dis1 output disable time sel133/100 cpu_div2 f (cpu) = 100 or 133mhz 8 10 ns t cpu div2 clock p eriod 2 f (cpu) = 100 mhz 20 20.08 20.4 ns t c cpu _ div2 clock period 2 f (cpu) = 133 mhz 15 15.06 15.3 ns cycle to cycle jitter f (cpu) = 100 or 133mhz 250 ps duty cycle f (cpu) = 100 or 133mhz 45 55 % t sk(p) cpu_div2 pulse skew f (cpu) = 100 or 133mhz 1.6 ns t 1 pulse duration width high f (cpu) = 100 mhz 7.1 ns t w1 p u lse d u ration w idth , high f (cpu) = 133 mhz 4.7 ns t 2 pulse duration width low f (cpu) = 100 mhz 7.3 8.9 ns t w2 p u lse d u ration w idth , lo w f (cpu) = 133 mhz 5 6.6 ns t r rise time v o = 0.4 v to 2.0 v 0.4 1.4 2 ns t f fall time v o = 0.4 v to 2.0 v 0.4 1.3 1.8 ns 2 the average over any 1- m s period of time is greater than the minimum specified period.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 11 post office box 655303 ? dallas, texas 75265 switching characteristics, v dd = 2.375 v to 2.625 v, t a = 0 c to 85 c (continued) apic parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 apic f (apic) = 16.67 mhz 6 10 ns t dis1 output disable time sel133/100 apic f (apic) = 16.67 mhz 8 10 ns t c apic clock period 2 f (apic) = 16.67 mhz 60 60.24 60.6 ns cycle to cycle jitter f (cpu) = 100 or 133 mhz 400 ps duty cycle f (apic) = 16.67 mhz 45 55 % t sk(p) apic pulse skew f (apic) = 16.67 mhz 3 ns t (off) apic clock to cpu clock offset, rising edge apic cpux 1.5 4 ns t w1 pulse duration width, high f (apic) = 16.67 mhz 25.5 28 ns t w2 pulse duration width, low f (apic) = 16.67 mhz 25.3 29.2 ns t r rise time v o = 0.4 v to 2 v 0.4 1.6 2.1 ns t f fall time v o = 0.4 v to 2 v 0.4 1.2 1.7 ns 2 the average over any 1- m s period of time is greater than the minimum specified period. switching characteristics, v dd = 3.135 v to 3.465 v, t a = 0 c to 85 c 3v66 parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 3v66x f (3v66) = 66 mhz 6 10 ns t dis1 output disable time sel133/100 3v66x f (3v66) = 66 mhz 8 10 ns t c 3v66 clock period 2 f (3v66) = 66 mhz 15 15.06 15.3 ns cycle to cycle jitter f (cpu) = 100 or 133 mhz 400 ps duty cycle f (3v66) = 66 mhz 45 55 % t sk(o) 3v66 bus skew 3v66x 3v66x f (3v66) = 66 mhz 50 150 ps t sk(p) 3v66 pulse skew 3v66n 3v66n f (3v66) = 66 mhz 2.6 ns t (off) 3v66 clock to cpu clock offset 3v66x cpux 0 0.75 1.5 ns t (off) 3v66 clock to pci clock offset, rising edge 1.2 2.1 3 ns t w1 pulse duration width, high f (3v66) = 66 mhz 5.2 ns t w2 pulse duration width, low f (3v66) = 66 mhz 5 ns t r rise time v o = 0.4 v to 2 v 0.5 1.5 2 ns t f fall time v o = 0.4 v to 2 v 0.5 1.5 2 ns 2 the average over any 1- m s period of time is greater than the minimum specified period.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 12 post office box 655303 ? dallas, texas 75265 switching characteristics, v dd = 3.135 v to 3.465 v, t a = 0 c to 85 c (continued) 48mhz parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 48mhz f (48mhz) = 48 mhz 6 10 ns t dis1 output disable time sel133/100 48mhz f (48mhz) = 48 mhz 8 10 ns t c 48mhz clock period 2 f (48mhz) = 48 mhz 20.5 20.83 21.1 ns cycle to cycle jitter f (cpu) = 100 or 133 mhz 500 ps duty cycle f (48mhz) = 48 mhz 45 55 % t sk(p) 48mhz pulse skew 48mhz 48mhz f (48mhz) = 48 mhz 3 ns t w1 pulse duration width, high f (48mhz) = 48 mhz 7.8 ns t w2 pulse duration width, low f (48mhz) = 48 mhz 7.8 ns t r rise time v o = 0.4 v to 2 v 1 2.1 2.8 ns t f fall time v o = 0.4 v to 2 v 1 1.9 2.8 ns 2 the average over any 1- m s period of time is greater than the minimum specified period. ref parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 refx f (ref) = 14.318 mhz 6 10 ns t dis1 output disable time sel133/100 refx f (ref) = 14.318 mhz 8 10 ns t c ref clock period 2 f (ref) = 14.318 mhz 69.84 ns cycle to cycle jitter f (cpu) = 100 or 133 mhz 700 ps duty cycle f (ref) = 14.318 mhz 45 55 % t sk(o) ref bus skew refx refx f (ref) = 14.318 mhz 150 250 ps t sk(p) ref pulse skew refn refn f (ref) = 14.318 mhz 2 ns t w1 pulse duration width, high f (ref) = 14.318 mhz 26.2 32.7 ns t w2 pulse duration width, low f (ref) = 14.318 mhz 26.2 31.2 ns t r rise time v o = 0.4 v to 2 v 1 2 2.8 ns t f fall time v o = 0.4 v to 2 v 1 1.9 2.8 ns 2 the average over any 1- m s period of time is greater than the minimum specified period.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 13 post office box 655303 ? dallas, texas 75265 switching characteristics, v dd = 3.135 v to 3.465 v, t a = 0 c to 85 c (continued) pci parameter from (input) to (output) test conditions min typ max unit t en1 output enable time sel133/100 pcix f (pci) = 33 mhz 6 10 ns t dis1 output disable time sel133/100 pcix f (pci) = 33 mhz 8 10 ns t c pcix clock period 2 f (pci) = 33 mhz 30 30.12 30.5 ns cycle to cycle jitter f (cpu) = 100 or 133 mhz 300 ps duty cycle f (pci) = 33 mhz 45 55 % t sk(o) pcix bus skew pcix pcix f (pci) = 33 mhz 70 300 ps t sk(p) pcix pulse skew pcin pcin f (pci) = 33 mhz 4 ns t (off) pcix clock to 3v66 clock offset 1.2 3 ns t w1 pulse duration width, high f (pci) = 33 mhz 12 ns t w2 pulse duration width, low f (pci) = 33 mhz 12 ns t r rise time v o = 0.4 v to 2 v 0.5 1.6 2 ns t f fall time v o = 0.4 v to 2 v 0.5 1.5 2 ns 2 the average over any 1- m s period of time is greater than the minimum specified period.
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 14 post office box 655303 ? dallas, texas 75265 parameter measurement information t r 3 v 0 v v ih_ref v t_ref v il_ref v t_ref v t_ref t plh t phl t f t w_high t w_low v oh v ol input output voltage waveforms r l = 500 w load circuit for t pd and t sk from output under test c l (see note a) r l = 500 w s1 v o_ref open gnd t plh /t phl t plz /t pzl t phz /t pzh open v o_ref gnd test s1 ?? t w input 3 v 0 v v ih_ref v t_ref v il_ref from output under test test point c l (see note a) load circuit for t r and t f voltage waveforms 0 v output waveform 2 s1 at gnd (see note b) voltage waveforms v oh v ol v dd v t_ref v t_ref v t_ref t pzl t plz t phz t pzh v t_ref v oh 0.3 v v ol + 0.3 v 3 v 0 v output waveform 1 s1 at 6 v (see note b) output enable (high-level enabling) notes: a. c l includes probe and jig capacitance. c l = 20 pf (cpux, apic, 48mhz, ref), c l = 30 pf (pcix) b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 14.318 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. parameter 3.3-v interface 2.5-v interface unit v ih_ref high-level reference voltage 2.4 2 v v il_ref low-level reference voltage 0.4 0.4 v v t_ref input threshold reference voltage 1.5 1.25 v v o_ref off-state reference voltage 6 4.6 v figure 3. load circuit and voltage waveforms
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 15 post office box 655303 ? dallas, texas 75265 parameter measurement information t sk(o) v t_ref cpux or pcix clock 3v66 or cpux cpux or pcix clock v t _ref v t_ref t (low) t (high) t c t sk(p) t plh t phl duty cycle t (low) t c 100 v t _ref t (off) [3v66 to pcix] t (off) [cpux to apic] t (off) [cpux to 3v66] 3v66, pcix, or apic figure 4. waveforms for calculation of skew, offset, and jitter ??????????? ??????????? ??????????? ??????????? ??????????? ???????????? cpu (internal) pci (internal) pwr_dwn pci (external) cpu (external) vco crystal note a: shaded sections on the vco and crystal waveforms indicate that the vco and crystal oscillators are active and there is a valid clock. figure 5. power-down timing
cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs scas634 july 28, 1999 16 post office box 655303 ? dallas, texas 75265 mechanical data dl (r-pdso-g**) plastic small-outline package 4040048 / d 08/97 48-pin shown 56 0.730 (18,54) 0.720 (18,29) 48 28 0.370 (9,40) (9,65) 0.380 gage plane dim 0.420 (10,67) 0.395 (10,03) a min a max 0.006 (0,15) nom pins ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) seating plane 0.020 (0,51) 0.040 (1,02) 25 24 0.008 (0,203) 0.012 (0,305) 48 1 0.008 (0,20) min a 0.110 (2,79) max 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) m 0.005 (0,13) 0.025 (0,635) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec mo-118
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